Failure analysis methods are essential for developing, manufacturing, and qualifying ICs. Many different types of failure analysis methods are available for locating and identifying defects and failure mechanisms in ICs to aid in IC process development, to aid in the manufacture of ICs, and to qualify ICs as being substantially defect-free for reliability assurance. Pinpointing of different types of defects and failure mechanisms in an IC generally requires the use of different analytical methods, since each analytical method has certain advantages and disadvantages. A general review of failure analysis methods can be found in an article entitled, "IC Failure Analysis: Techniques and Tools for Quality and Reliability Improvement," by J. M. Soden and R. E. Anderson, Proceedings of the IEEE, Vol. 81, pp. 703-715 (1993). Additionally, the detection of defects and failure mechanisms in ICs becomes increasingly difficult as each succeeding generation of ICs becomes more complex with reduced feature sizes, reduced conductor line widths, and an increased number of interconnecting layers. As a result, there is a continuing need for the development of new and improved IC failure analysis apparatus and methods.
One particular IC failure analysis method, applicable to the testing of complementary metal-oxide semiconductor (CMOS) ICs, is quiescent power supply current (I.sub.DDQ) testing. This method, which has been used for many years and is receiving wider acceptance in the industry, is disclosed in a review article entitled, "I.sub.DDQ Testing: A Review," by J. M. Soden, C. F. Hawkins, R. K. Gulati and W. Mao, Journal of Electronic Testing: Theory and Applications, Vol. 3, pp. 291-303 (1992). The I.sub.DDQ method is also disclosed in U.S. Pat. No. 5,519,333 to Righter, which is incorporated herein by reference.
I.sub.DDQ testing is based on the principle that CMOS lCs are designed to provide a very small quiescent power supply current drain due to leakage that is on the order of about 100 nanoamperes (nA), depending on the level of complexity of the particular IC. In a quiescent state, all circuit nodes in a CMOS IC have voltages that are settled to steady state levels, with a logical high level (i.e. a "1" state) typically being at the power supply voltage level. When a logic transition occurs in the IC due to an applied input voltage, there is a momentary period of time (generally less than about one microsecond) during which complementary n-type and p-type transistors in a plurality of gates within the IC are switched, resulting in a momentary large current drain on the power supply. The transient current (denoted I.sub.DDT) during this brief time can be up to hundreds of milliamperes (mA) or more. Within this transient switching time period, some of the transistors will be switched on and their complementary transistors switched off. After this, the current from the power supply will again settle down to the I.sub.DDQ level.
The presence of a defect (e.g. a gate-to-source oxide electrical short circuit) in a transistor in the CMOS IC can be determined from a measurement of the quiescent current, I.sub.DDQ, using measurement circuitry placed in line with the power supply connection to the IC since activation of the transistor containing the short circuit will result in an increase in the quiescent current, I.sub.DDQ. In order to activate a portion (or ideally all) of the transistors in the IC to assess its reliability, a set of test vectors corresponding to different logical inputs to the IC are used. By measuring the quiescent current, I.sub.DDQ, as each vector in the set of test vectors is provided to the IC (i.e. toggling of the IC) and comparing the measured I.sub.DDQ signals to results from a known-good IC (i.e. a defect-free IC), the presence of any defects in the IC being tested can be ascertained.
A disadvantage of the I.sub.DDQ failure analysis method is that it requires that analog measurement circuitry be provided in line with the power supply current connection to the IC. The analog measurement circuitry must generally be capable of measuring quiescent currents of less than one microampere (.mu.A) at clock rates of tens of kHz or more. The same measurement circuitry must be capable of passing the orders of magnitude larger transient current, I.sub.DDT, during switching transients wherein the logic states in the IC are switched in response to the set of applied test vectors. As the complexity (i.e. the number of transistors) in an IC increases with each new generation of ICs, both the quiescent current, I.sub.DDQ, and the transient current, I.sub.DDT, increase, placing additional demands on the measurement circuitry.
An advantage of the defect testing apparatus and method of the present invention is that an increased measurement sensitivity can be achieved for analyzing one or more ICs by measuring a transient voltage component (V.sub.DDT) of the operating voltage (V.sub.DD) of the IC as compared to current measurements using the conventional I.sub.DDQ method. V.sub.DDT signals obtained using the apparatus and method of the present invention can be up to several orders of magnitude more sensitive than current signals measured for the same IC by the I.sub.DDQ method.
Another advantage of the present invention is that measurement sensitivity is substantially unaffected by the complexity of the ICs to be tested. This is in contrast to I.sub.DDQ testing which can become increasingly difficult as the complexity of the ICs to be tested increases.
A further advantage of the present invention is that no measurement circuitry must be placed in-line with the electrical connection between the power supply source and the IC to be tested. This can simplify electrical interconnections to the IC, and increase testing throughput.
Still another advantage of the present invention is that a wider range of IC designs are testable since the ICs need not be expressly designed for I.sub.DDQ testability.
These and other advantages of the method of the present invention will become evident to those skilled in the art.